1. Field of the Invention
The present invention relates to a semiconductor device and an information processing system including the same, and more particularly to a semiconductor device that can issue a command signal and the like at timing different from that of a chip select signal and an information processing system including the same.
2. Description of Related Art
Semiconductor memory devices typified by a dynamic random access memory (DRAM) receive an address signal and a command signal supplied from a controller, and access the memory cell array based on the signals. The address signal and the command signal are enabled when a chip select signal supplied from the controller is activated. In principle, the controller therefore needs to issue the address signal and the command signal with the chip select signal activated.
DDR4 (Double Data Rate 4) DRAMs have recently been proposed as DRAMs even faster than DDR3 (Double Data Rate 3) DRAMs. DDR4 DRAMs support a new function called “CS_n to command address latency (CAL latency)”. The CAL latency means that the controller supplies an address signal and a command signal to a semiconductor device after a predetermined time (predetermined latency) since the controller supplies a chip select signal to the semiconductor device and the semiconductor device receives the address signal and the command signal after a predetermined time (predetermined latency) since the reception of the chip select signal. That is, the CAL latency is a function that allows input of the address signal and the command signal after a lapse of a predetermined latency since the reception of the chip select signal with respect to the semiconductor device. Such a function can be used to grasp the input timing of the address signal and the command signal on the semiconductor device (semiconductor memory device) side. Address receivers and command receivers can thus be deactivated in periods where the address signal and the command signal are not input. This allows a reduction in power consumption.
A semiconductor device that can issue a command signal and the like at timing different from that of a chip select signal is also described in Japanese Patent Application Laid-Open No. 2000-285674.
What timing to change the address receivers and the command receivers from an inactive state to an active state after a lapse of the CAL latency since the activation of the chip select signal, and what timing to change the receivers from an active state to an inactive state, may be determined in consideration of the CAL latency and power consumption. There are three important factors concerned, including the power consumption of the receivers, the power consumption caused by control signals for controlling the activation and deactivation of the receivers, and the value of the CAL latency.
For example, Japanese Patent Application Laid-Open No. 2000-285674 discusses that an enable signal is activated at timing ½ clock cycles after the activation of a chip select signal, and the enable signal is deactivated at timing one clock cycle later. According to the semiconductor device described in Japanese Patent Application Laid-Open No. 2000-285674, the enable signal has a waveform that changes with the chip select signal. If the chip select signal changes frequently in a short period, the enable signal also changes frequently in a short time. In such a case, the semiconductor device fails to provide a sufficient effect for reducing power consumption including the charging and discharging currents of the enable signal. The reason is that the enable signal, supplied to a large number of address receivers and command receivers, is a high-load internal signal in the semiconductor device.